Staff Verification Engineer
Mar 29, 2019 Xilinx Inc. ,   San Jose, CA, United States

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Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI). 

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!


Verification and Validation

  • Lead and plan verification of complex digital design blocks by fully understanding the architecture and design specification
  • Interact with architects and design engineers to create a comprehensive verification testplan
  • Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
  • Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
  • Debug tests with design engineers to deliver functionally correct design blocks
  • Identify and write coverage measures for stimulus quality measurements
  • Perform coverage analysis to identify verification holes and achieve closure on coverage metrics


Education and Experience Requirements 


  • BS with 8+ years of experience or MS with 6+ years of experience or PhD with 3+ years of experience with a degree in electrical engineering, computer engineering or related equivalent 
  • Strong experience in HDL, verification, and general computational logic design/verification concepts
  • Experience in ASIC design flow from frontend to backend is a plus.
  • Proficiency in System Verilog and UVM
  • Prior use of simulation tools/debug environments such as Synopsys VCS, Synopsys VCS-XA, Cadence IES or Mentor Questa is required
  • Proficiency in Perl, Python and/or other scripting language
  • Understanding of DFT, ijtag experience is a plus
  • Understanding of AMBA protocols like AXI4, AXI-STREAM and AHB is a strong plus
  • Basic understanding of formal property checking, gate level simulation, power verification using UPF, reset verification, and/or contention checking is a plus
  • Excellent interpersonal skills, self-motivated