Senior Physical Design Engineer (ASIC/SoC Place & Route)
Aug 25, 2018 TSMC North America,   San Jose or Austin

Job description

Location: San Jose or Austin


Responsibilities:
  • Perform the following:
    • Block level floorplan
    • Clock tree synthesis
    • Place & Route
    • RC extraction
    • STA, timing closure
    • IR/EM analysis and fix
    • DRC/LVS/ERC clean up
    • Tape-out sign off
  • Customer on-site support

Desired Skills and Experience

Requirements:
  • Bachelor/Master’s degree in Electrical Engineering or Computer Science
  • 5+ years Netlist (or RTL)-GDS physical implementation experience
  • In depth knowledge of major EDA tools/design flows
  • Experience with TSMC N28 or below technology
  • Experience in block level implementation or chip integration and signoff
  • Experience in Perl/TCL language programming
  • Proven record in multi-million gate design production tapeouts
  • Experience in any of the following is a plus:
    • TSMC N16 and below technology
    • Low-power implementation methodology
    • Advanced timing signoff methodology
    • Independently complete Netlist-GDS P&R, signoff task

Personal Attributes:
  • Aggressive in learning and problem-solving
  • Good communication skill and a good team player
  • Self-motivated and can work independently

TSMC Technology is an Equal Opportunity Employer.


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