CAISS 2018 Spring Symposium: Present and Future of MRAM
Mar 31, 2018

In between HDD and NAND, where does STT-MRAM stand and where will it go? Come and listen to Dr. Yiming Huai and Dr. Luc Thomas, two STT-MRAM pioneers and storage experts, talking about STT-MRAM applications and futures.

Agenda:

  • 2-2:30pm: Registration and Networking
  • 2:30-3pm: Welcome from CAISS President and introduce 2018 BOD team
  • 3:00 – 4:00pm Speeches:

3:00 – 3:30: STT-MRAM: ON THE CUSP OF MASS PRODUCTION, Yiming Huai, VP, Avalanche Technology

3:30 -4:00: STT-MRAM for embedded memory applications from eFlash replacement to Last Level Cache, Luc Thomas, principal technologist, TDK-Headway Technologies

  • 4:00-4:30: Panel Discussion
  • 4:30-5:00: networking


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Speaker #1: Yiming Huai, Vice President of Technology/Foundry, Avalanche Technology,

Title: STT-MRAM: ON THE CUSP OF MASS PRODUCTION

Abstract: Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a leading emerging nonvolatile memory for embedded memory applications and for persistent memory in new market applications owing to its unique performance combination of fast read and write speed (<10ns), high endurance (1016), and non-volatility. While STT-MRAM technology is on the cusp of mass production, critical technical and manufacturing challenges remain. In addition to the continued advance in perpendicular magnetic tunnel junction (pMTJ) performance, advanced process development is increasingly pivotal for manufacturing yield improvement.

This talk will review current status of STT-MRAM product devolvement and manufacturing, and highlight key items in critical path for successful STT-MRAM mass production. Write error rate, read disturb, read/write endurance, and data retention of Avalanche’s fully functional 64Mbit chip will be presented. We also discuss the market entry of the STT-MRAM. While it is currently being targeted for stand-alone memory (replacing nvSRAM and persistent DRAM) and embedded memory (replacing embedded Flash, SRAM and DRAM), new market applications such as storage-class solid state drives and unified NVM solutions are also being explored.

We will also present a 3D cross-point STT MRAM architecture utilizing a novel two-terminal bipolar threshold selector. We have demonstrated the integrated device performance of the selector and the state-of-the-art perpendicular MTJ. This effectual combination of selector and pMTJ provides a path to realize 3D STT-MRAM high density storage class memory (~100Gb). Finally, we will compare STT MRAM with other NVM technologies such as RRAM in term of production readiness and different market applications.

Bio: Dr. Yiming Huai serves as VP of Technology and Foundry Partnership at Avalanche Technology, a front runner to commercialize STT MRAM technology. He leads Avalanche STT MRAM product development and manufacturing in collaboration with top-tier foundries and also plays a key role in business development.

Dr. Huai is a pioneer on STT MRAM and was the first to demonstrate spin transfer switching in magnetic tunnel junctions. Dr. Huai received his BS degree in theoretical physics from Shanghai University of Science and Technology and his M.S. and Ph.D. in Physics from the University of Montreal. He worked as a Staff Scientist at the Lawrence Livermore National Laboratory and as a Post-Doctoral Fellow at the National Research Council in Ottawa, Canada. From 1996 to 2001,

Dr. Huai served as Sr. Director of Thin Film Manufacturing at Read-Rite Corporation (now Western Digital), where he led the development and volume production of industry leading GMR heads for hard disk drives. In 2002, Dr. Huai cofounded Grandis, Inc., a pioneer in STT MRAM technology and served as CTO, VP of Engineering and board member. While at Grandis, Dr. Huai successfully raised more than $25M in private and government (DARPA STT MRAM and NIST) funding and led STT MRAM joint development with leading semiconductor companies (Renesas and Hynix). Grandis was acquired by Samsung in 2011. He has published more than 150 papers in scientific journals, and holds more than 160 U.S. patents. He has given more than 60 invited talks on STT-MRAM technology and has served as Conference Chairman and Organizer for major international magnetic and semiconductor conferences and workshops. Dr. Huai was an Editorial Board member of Spin Journal. In 1996, Dr. Huai received the prestigious R&D 100 Award for his innovative work on Ultra-High Density Magnetic Sensors.

Speaker #2: Luc Thomas, principal technologist, TDK-Headway Technologies

Title: STT-MRAM for embedded memory applications from eFlash replacement to Last Level Cache

Abstract: Recent advances in embedded Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) have overcome major technological hurdles and demonstrated the viability of the technology, opening the way to mass production. In this talk, we will review these advances and discuss how the physics of STT-MRAM allows tailoring the technology to emphasize retention, speed and endurance, thus enabling a wide range of applications, from embedded Flash to working memory and Last Level Cache (LLC).

Bio: Luc Thomas is the principal technologist in charge of device physics in the STT-MRAM group at TDK-Headway Technologies, which he joined in late 2012. Prior to joining TDK, Dr. Thomas was Research Staff Member at the IBM Almaden Research Center, where he worked on the current-driven dynamics of magnetic domain walls and their application to Racetrack Memory.

Dr. Thomas received a Ph.D in physics from Joseph Fourier University in Grenoble, France, in 1997. He is the author of more than 90 papers and patents on the physics and technology of magnetic devices. He was elected fellow of the American Physical Society in 2012.


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